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cxa1203m/n 8mm vcr pal jog description the cxa1203m/n compensates the color alignment in variable speed mode for pal-system 8mm vcrs. this ic is also available for the secam system with the built-in secam detector and bell and c-bell filters. features color alignment compensation which does not require 1h delay line no afc (f h ) adjustment necessary built-in secam detector built-in bell and c-bell filters available for the pal-m system functions v-invert circuit, th/dl apc, 2fsc pll, sq det, ex burst circuit, afc (f h ), timing generator, secam detector, bell filter, c-bell filter structure silicon monolithic ic absolute maximum ratings (ta = 25?) supply voltage v cc 7.0 v operating temperature topr ?0 to +75 ? storage temperature tstg ?5 to +150 ? allowable power dissipation p d cxa1203m 567 mw cxa1203n 536 mw recommended operating conditions supply voltage 4.5 to 5.5 v (5.0v typ.) ?1 e01z33-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. cxa1203m 24 pin sop (plastic) cxa1203n 24 pin ssop (plastic)
?2 cxa1203m/n block diagram and pin configuration pb pb rec (se) pb (pal) pb (se) rec th/dl swd 1/2fhm th/dl (1/2fhta) pal-m bf bf pal-m pal cw bf xch th/dl (1/2fhta) dl th xpb mask 75 1 mask 75 2 u erri 1/2fhm pal-m th/dl xfhm 1/2fhm 1/2fhm sa cont clg pls clp pls swd 1/2fht 1/2 fht secam detpls test rst normal secam bell in secam in h id normal 1/2fhtab swd1/2fhm swd1/2fht d erri xshp bell filter 24 adj 23 bell in 22 mode 21 secam in 20 dl gain adj 19 fsc in 18 sq id 17 dl apc lpf 16 c out 15 iref 14 vreg 13 v cc 1 pb c in 2 secam ack 3 1/2fhmp 4 75% c 5 dldp 6 secam jump 7 secam lpf 8 afc lpf 9 hd 10 c sync 11 gnd 12 mode c-bell bell amp 90 vco s/h peak hold lpf2 s/h 75% mask2 75% mask1 edge trig edge trig secam p. d. jump p. d. hd afc id d v-i1 2 sq p.d. lpf1 lpf cont clamp lpf1 fm demod lpf3 conv1 dummy lim lim1 lim2 v-i2 lpf2 sw main sw bf gen 75% 150% d 1/2 d
3 cxa1203m/n pin description pin no. symbol 1v cc 5.0v (typ.) supply voltage pin 2 pb c in 350mvp-p 150mvp-p (burst) input pin of pal playback chrominance signal. the chroma ack operates to cut off the output at pin 15 when the dc bias voltage at pin 2 is 0.7v or less. 3 secam ack 3.8v (h) 0v (l) secam detector output pin. h secam l pal the secam or pal mode is fixed by applying an external dc voltage. secam: 3.0 to 5.0v pal: 0 to 1.0v 4 1/2 fhmp output pin of the pulse obtained by dividing down the afc (f h -pll) output by 2. 5 75% c connecting pin of the charging and discharging capacity to produce the triangular wave chronized with the c sync signal. all timing pulses used in the ic are produced from this triangular wave. voltage equivalent circuit description dc ac 3.2v 1.7v 3.5v 1.0v 3.0v 60k 47k 15.2p 2 pr v cc v cc 3 20k 20k 10k 8k pr (sub) 4 4k/2 ( 2) ( 2) pr v cc 5 20k/3 ( 3) (sub) ( 3) 28k 8k pr v cc
4 cxa1203m/n pin no. symbol 6 dldp 1.4vp-p input pin to switch the polarity of the 1/2fht pulse for the secam detector. output pin of the afc id signal in test mode ? 1 . 7 secam jump 2.8v (h) 1.4v (l) 2.8v (h) 1.4v (l) 1.4vp-p output pin to switch the polarity of the 1/2fht pulse. mode selection ? 1 is possible by applying an external dc voltage. pal-m: 0 to 0.5v normal: open reset: 3.6 to 4.1v test: 4.3 to 5.0v 8 secam lpf 2.5v connecting pin of the time constant of the lpf for the secam detector. 9 afc lpf 2.0v connecting pin of the time constant of the lpf for the afc (f h -pll). voltage equivalent circuit description dc ac 6 8k pr v cc 10k 10k 20k 20k 100k 7 pr (sub) v cc 8 4k 4k pr (sub) 2k 100k v cc 9 4k/2 10k 6.5k 10k pr 20k 1k 1k (sub) (sub) ( 2) ( 4) v cc
5 cxa1203m/n pin no. symbol 10 hd output pin of the hd pulse produced in the afc (f h -pll). 11 c sync input pin of the composite sync signal. the internal threshold voltage is 2.0v and the polarity is active high. gnd pin 13 vreg 4.2v output pin of the regulated voltage source in the ic (4.2v). 14 iref 2.1v connecting pin of the standard resistance to produce the reference current source in the ic. voltage equivalent circuit description dc ac 10 20k pr 1k ( 2) (sub) ( 2) v cc 11 pr 20k 46k 20k 13 23p connected to about 30 elements ( 32) v cc 14 10k pr (sub) ( 2) iref 4k 40k 8k v cc 4.0v 0.4v 2.0v 12 gnd
6 cxa1203m/n pin no. symbol 16 dl apc lpf 2.4v connecting pin of the time constant of the lpf for the th/dl apc loop. the th/dl lock phase can be varied by applying an external dc current. 17 sq id 4.0v (h) 0v (l) 350mvp-p output pin of the sq detector. the th or dl output signal at pin 15 can be selected by applying an external dc voltage. dl: 0 to 2.0v th: 3.0 to 5.0v 18 fsc in input pin of the fsc. (chrominance subcarrier) voltage equivalent circuit description dc ac 16 pr pr v cc 17 10k pr 8k 20k (sub) v cc 18 pr 4k 30k 10.4p v cc in pal mode 350mvp-p 150mvp-p (burst) 15 c out 2.1v output pin of the playback pal signal (th, dl and ex burst) ? 2 , secam signal and pal-m signal. ( 4) 15 pr 2.5k v cc
7 cxa1203m/n pin no. symbol 21 mode mode selection ? 1 is possible by applying an external dc voltage. rec: 0 to 1.3v pb: 1.7 to 2.8v jog: 3.2 to 5.0v 22 bell in 83mvp-p (secam burst) 117mvp-p (pal burst) input pin of the secam signal. input pin of the secam detector in playback mode. voltage equivalent circuit description dc ac 21 pr 8k (sub) v cc 22 pr 13.5k 15k 38k 15.2p 15.2p 100k 4k v cc 150mvp-p (burst) 19 dl gain adj 5.0v (typ.) control pin of the dl signal gain. the gain can be varied by applying an external dc voltage. the internally fixed gain is obtained at 5.0v. output pin of the s/h circuit in test mode. 20 secam in input pin of the secam detector in rec mode. 19 13.4k 2670 13.4k pr 15k v cc 20 pr 10k 40k 20k 15.2p v cc
8 cxa1203m/n pin no. symbol 23 adj 5.0v (typ.) ex burst phase adjustment pin. the phase can be varied by applying an external dc voltage. the internally fixed phase is obtained at 5.0v. vco output pin in test mode. 24 bell filter 3.0v connecting pin of the time constant of the bell and c-bell filters. voltage equivalent circuit description dc ac 23 10k 38k 38k pr 30k (sub) ( 2) v cc 2k 24 4k 200 70 1k ( 5) ( 3) ( 2) notes) ? 1 refer to mode description. ? 2 pal playback signal (th, dl and ex burst) the dl signal is symmetrical to the th signal (pal playback signal) about the b-y axis. the burst signal produced from the fsc (chrominance subcarrier) in the ic is known as the ex burst. the ex burst is inserted into the playback chrominance signal in jog mode.
9 cxa1203m/n mode description mode pal secam pal-m reset test dl th rec pb jog control pin pin 3 pin 7 pin 17 pin 21 voltage 0 to 1.0v high impedance 3.0 to 5.0v 0 to 0.5v 3.6 to 4.1v 4.3 to 5.0v 0 to 2.0v high impedance 3.0 to 5.0v 0 to 1.3v 1.7 to 2.8v 3.2 to 5.0v description fixed pal mode automatic selection of pal or secam fixed secam mode the pal-m signal is output from pin 15 by inputting an ntsc signal to pin 2. (for details, see "notes on use".) the logic block (afc id, 150% masking and 1/2 division) in the afc (f h -pll) is turned off. the operation of the afc id, vco and s/h blocks in the afc (f h -pll) is checked. the dl signal is output from pin 15. the th or dl signal selected by the sq detector decision is output. the th signal is output from pin 15. rec mode playback mode the ex burst is inserted into the original burst signal portion in pal playback mode.
10 cxa1203m/n electrical characteristics (ta = 25 c, v cc = 5.0v, see fig. 1. electrical characteristics test circuit.) no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 item circuit current (pal pb) circuit current (secam rec) vreg (5.0v) vreg (4.5v) vreg (5.5v) v (iref) input sw crosstalk (secam rec) input sw crosstalk (secam pb) bell filter gain c-bell filter gain th amp gain th/dl amp gain ratio th/dl phase difference th/exb level ratio ex burst level ratio ex burst phase difference th-ex burst phase difference symbol i cc (pp) i cc (sr) vreg (5.0) vreg (4.5) vreg (5.5) v (iref) i-ct (sr) i-ct (sp) bf-g cbf-g tha-g da-g th-dl ? v th-exb ? v exb ? exb th-exb sw1 sw2 sw3 sw4 sw5 o o o o 5.0v 4.5v 5.5v 5.0v 2.5v 1.0v 3.0v 1.0v 3.0v 1.0v 3.0v 2.0v 1.7v 1.3v 1.7v 1.3v 1.7v 1.3v 1.7v 2.8v 3.2v bias condition v cc v 2 v 3 v 7 v 17 v 21 a a e f g h g h g test point pal pb secam rec pal pb secam rec secam pb secam rec secam pb pal pb pal jog dc current test dc voltage test c out output level test c out output level test c out output level test (4.43mhz) c out phase test output level test c out phase test 17.5 20.0 4.10 4.10 4.10 2.05 11.0 3.0 2.5 0.6 50 1.1 1.0 90 40 25.5 27.0 4.24 4.24 4.24 2.12 38.0 53.0 14.0 0 0.3 0.4 90 2.6 0 96 48 32.5 34.0 4.40 4.40 4.40 2.20 35.0 45.0 16.0 3.0 2.0 1.4 120 4.1 1.0 102 56 ma ma v v v v db db db db db db deg db db deg deg output waveform and test content min. typ. max. unit mode switch condition on : o, off: blank
11 cxa1203m/n no. 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 item pal-m dl apc loop characteristics pal-m ex burst level ratio pal-m ex burst phase difference pal-m dl-ex burst phase difference sq det +v detection sq det v detection main sw crosstalk (th) afc hd timing afc hd width afc lock range (1) afc lock range (2) timing ex burst delay timing ex burst width timing 1/2fhmp delay timing 1/2fhmp duty symbol dl-apc (pal m) ? v exb (pal m) ? exb (pal m) th-exb (pal m) sq (+) sq ( ) msw-ct (th) hd-d hd-w afc-lr (1) afc-lr (2) exb-d exb-w 1/2fh-d 1/2fh-du switch condition on : o, off: blank sw1 sw2 sw3 sw4 sw5 o o o o o o o o o 5.0v 2.5v 1.0v 5.0v 3.8v 0v 3.0v 2.8v 1.7v 3.2v 1.7v bias condition v cc v 2 v 3 v 7 v 17 v 21 g i g d g c test point pal-m pb pal reset pal pb pal jog pal pb c out phase test c out output level test c out phase test dc voltage test at pin 17 c out output level test time test at pin 10 frequency test at pin 10 time test 100 1.5 104 20 122 35 3.0 4.4 55 55 4.5 3.9 32.0 44 90 0 96 10 49 1.2 5.3 5.2 4.4 36.0 50 80 1.5 88 0 98 59 44 0.3 6.2 55 55 5.8 5.1 40.0 56 deg db deg deg deg deg db s s hz hz s s s % output waveform and test content min. typ. max. unit mode
12 cxa1203m/n bias condition switch condition on : o, off: blank no. 33 34 item secam detector demod (pb ) ack check symbol sq (pb) ack sw1 sw2 sw3 sw4 sw5 o o 5.0v 2.5v 0.5v 1.0v 5.0v 2.8v v cc v 2 v 3 v 7 v 17 v 21 b g test point pb pal pb dc voltage test at pin 3 c out output level test 3.60 3.80 58 4.00 49 v db output waveform and test content min. typ. max. unit mode
13 cxa1203m/n 4.286mhz cw 350mvp-p cw delayed by 135 from vfsc 350mvp-p cw delayed by 135 from vfsc 150mvp-p input signal v pal 4.286mhz cw 350mvp-p 4.286mhz cw 32mvp-p 4.286mhz cw 83mvp-p v se 15.625khz, 4.0vo-p vsync 4.43mhz cw 350mvp-p vfsc test the dc voltage at pin 13. test the dc voltage at pin 13. test the dc voltage at pin 13. test the dc voltage at pin 14. 20 log { } 20 log { } 20 log { } 20 log {} 20 log {} dl th test content 5 s 64 s c out (4.286mhz component) v se c out (4.286mhz component) v pal c out (4.286mhz component) v se c out (4.43mhz) v pal output level of t11 c out (4.43mhz) test methods of electrical characteristics no. item 1 2 3 4 5 6 7 8 9 10 11 12 13 circuit current (pal pb) circuit current (secam rec) vreg (5.0v) vreg (4.5v) vreg (5.5v) v (iref) input sw crosstalk (secam rec) input sw crosstalk (secam pb) bell filter gain c-bell filter gain th amp gain th/dl amp gain ratio th/dl phase difference
14 cxa1203m/n cw delayed by 90 from vfsc 150mvp-p input signal v pal v se 15.625khz, 4.0vo-p 15.734khz, 4.0vo-p vsync 4.43mhz cw 350mvp-p 3.58mhz cw 350mvp-p vfsc 20 log {} 7.4db ? v (eb) = 20 log {v (eb1) /v (eb2) } ? (eb) = 2 1 th test (dl) on the basis of vfsc. ? v (eb) = 20 log {v (eb1) /v (eb2) } ? (eb) = | 1 2 | t18 test content t11 (p-p) (eb1 + eb2)/2 eb1 eb2 eb1 130mvp-p eb2 eb1 eb2 yc mix c sync 5 s 5 s 64 s eb1 eb2 vfsc 2 1 eb1 eb2 eb1 eb1 eb2 vfsc 2 1 yc mix c sync 5 s 130mvp-p 1 + 2 2 1 + 2 2 phase difference between the center of ex burst and th signal. phase difference between the center of ex burst and dl signal. no. item 14 15 16 17 18 19 20 21 th/exb level ratio ex burst level ratio ex burst phase difference th-ex burst phase difference pal-m dl apc loop characteristics pal-m ex burst level ratio pal-m ex burst phase difference pal-m dl-ex burst phase difference 5 s 64 s 5 s 63.6 s
15 cxa1203m/n signal with the phase delayed from vfsc 150mvp-p signal with the phase delayed from vfsc 150mvp-p input signal v pal v se 15.625khz, 4.0vo-p 19.0khz 15.625khz, 4.0vo-p vsync 4.43mhz cw 350mvp-p 4.43mhz cw 350mvp-p vfsc test the phase of v pal (on the basis of vfsc) when dc is changed from l to h (4.0v) at pin 17. test the phase of v pal (on the basis of vfsc) when dc is changed from h to l (0v) at pin 17. test by th signal timing. test the time at pin 10. test the frequency at pin 10. test the time at c out. test content no. item 22 23 24 25 26 27 28 29 30 sq det +v detection sq det v detection main sw crosstalk (th) afc hd timing afc hd width afc lock range (1) afc lock range (2) timing ex burst delay timing ex burst width 4.0v 5.0 s 11.0khz tw 3.5v 0v 2.0v c sync hd td t 3.5v 0v c out c sync td tw ( input frequency ) 1 t td tw td tw
16 cxa1203m/n 4.43mhz cw 350mvp-p input signal v pal secam signal (burst level 83mvp-p) v se 15.625khz, 4.0vo-p vsync vfsc test the time at pin 4. test the dc voltage at pin 3. c out (4.43mhz) v, 20 log (v/350mv) test content no. item 31 32 33 34 timing 1/2fhmp delay timing 1/2fhmp duty secam detector demod (pb ) ack check 1/2fhmp c sync t 1 t 2 td td t 1 (t 1 + t 2 )
17 cxa1203m/n fig. 1. electrical characteristics test circuit 5v 5v 5v 20k 5v 20k 2k 100k 50k v21 50k 1 820 39 1.2k 33p 0.1 1k 0.01 sw4 sw5 v se vfsc v17 10 1500p 100k 4.43mhz bpf 0.1 50k 10k 10k 5k 4.7k 4.7 v pal 0.01 110p 0.047 1000p sw2 vsync 3.3 v7 v3 sw1 v2 v cc sw3 pb pb rec (se) pb (pal) pb (se) rec th/dl swd 1/2fhm th/dl (1/2fhta) pal-m bf bf pal-m pal cw bf xch th/dl (1/2fhta) dl th xpb mask 75 1 mask 75 2 u erri 1/2fhm pal-m th/dl xfhm 1/2fhm 1/2fhm sa cont clg pls clp pls swd 1/2fht 1/2 fht secam detpls test rst normal secam bell in secam in h id normal 1/2fhtab swd1/2fhm swd1/2fht d erri xshp mode c-bell bell amp 90 vco s/h peak hold lpf2 s/h 75% mask2 75% mask1 edge trig edge trig secam p. d. jump p. d. hd afc id d v-i1 2 sq p.d. lpf1 lpf cont clamp lpf1 fm demod lpf3 conv1 dummy lim lim1 lim2 v-i2 lpf2 sw main sw bf gen 75% 150% d 1/2 d bell filter 24 adj 23 bell in 22 mode 21 secam in 20 dl gain adj 19 fsc in 18 sq id 17 dl apc lpf 16 c out 15 iref 14 vreg 13 e c d b a f h g v cc 1 pb c in 2 secam ack 3 1/2fhmp 4 75% c 5 dldp 6 secam jump 7 secam lpf 8 afc lpf 9 hd 10 c sync 11 gnd 12
18 cxa1203m/n description of functions 1. gain adjustment amplifier (dl signal) this amplifier adjusts the gain of the dl signal in pal or pal-m mode. the amplifier gain varies according to the dc voltage applied to pin 19. when 5v is applied to pin 19, the internally fixed gain is obtained and the levels of the th signal and the dl signal (4.43mhz component in pal mode, 3.58mhz component in pal-m mode) become the same. 2. fsc ?0 pll, 2 and ex burst block fig. 2 the fsc 90 pll consists of the 90 phase shifter, multiplier, lpf (low pass filter) 1 and v/i converter. a signal delayed by 90 to the fsc is obtained in this pll. by changing the dc voltage at pin 23, the amount of phase shift is varied. allowing adjustment of the phase of the ex burst and the duty (dc offset) of the 2fsc. by applying 5v at pin 23, the internally fixed phase shift is obtained. the 2fsc is produced from the multiplier output ( 2 output). the ex burst is produced by adding the fsc (or inverted fsc) to the fsc with 90 delay produced in the 90 pll. the fsc and the inverted fsc are switched in a period of 1/2f h , so the phase of the ex burst changes every 1h. 18 23 lim 90 v i lpf1 fsc cos t 2fsc cos (2 t 90 ) ex burst 2 cos ( t 45 ) 2 cos ( t 135 ) cos ( t 90 ) cos ( t 180 ) cos t 1/2f h cos t adj
19 cxa1203m/n fig. 4 the above figure shows the relation between the phase of the burst signal, the phase of the fsc (fsc) and the output at pin 17 (sq). as shown in the figure, the hysteresis angle is about 64 . if the relation is as shown in the figure below, the detector judges it as the correct sequence and set the output at pin 17 to high. fig. 5 therefore, the center phase of the burst signal (about the b-y axis) should be 90 to the fsc. 3. sq det (sequence detector) fig. 3 the sq det detects the color alignment of the chrominance signal. the sq pd is the phase detector which operates for a burst period only. this detects the color alignment by comparing the phase of the fsc signal inverted every 1h with the phase of the burst of the chrominance signal. 1/2f h fsc sq p.d. lpf3 chrominance signal burst flag gate 17 sq 180 135 90 112 48 0 +48 +90 +135 +180 +112 4v output at pin 17 phase of the burst signal (on the bias of fsc and fsc) 0v b-y fsc 135 burst b-y fsc +135 burst
20 cxa1203m/n fig. 7 the v-invert circuit constructs the th/dl apc loop that keep the phase difference between the burst of the th signal and the burst of the dl signal to be 90 . this circuit detects the phase of the bursts of the th and dl signals and varies the delay time of the phase shifter with reference to the error current of apc loop. in pal-m mode, the apc is applied to the fsc and the dl signal. therefore, the input burst signal has a phase of 90 to the fsc. the conv1 is a multiplier to obtain the dl signal. the dummy supplies the same gain loss and the same phase delay as produced in conv1 to the th signal so that there is no gain and phase difference between the th signal and the dl signal. the main sw outputs the th or dl signal according to the th/dl select signal (output at pin 17). when a bf xch pulse is supplied (in jog mode only), the ex burst is output. 4. v-invert (v axis inversion circuit) for color alignment, the dl signal which is produced by inverting the chrominance signal (th signal) about the b-y axis is necessary. the v-invert block produces the dl signal from the th signal. fig. 6 shows the principle of the v-invert block. fig. 6 define the b-y axis of the playback chrominance signal as cos t and input the playback chrominance signal and the 2fsc (cos 2 t) to the multiplier. by means of the frequency conversion of the 2fsc, the input chrominance signal is inverted about the b-y axis. the three fold frequency component (cos 3 t) is also output, but this component is rejected by the bpf in a later stage. fig. 7 shows the actual v-invert block. 2 fsc (cos t) cos 2 t dl: cos ( t ) cos (3 t ) th: cos ( t ) to y/c mix block rejected by the bpf. bpf playback chrominance signal cos ( t ) v-i lpf2 conv1 dummy 2fsc bf gate ex burst fsc pal-m pal th/dl bf xch main sw swd 1/2f h c out th dl 15 playback chrominance signal
21 cxa1203m/n fig. 8 the afc id compares the c sync frequency with the vco frequency. when a frequency difference is present, the afc id outputs an up or down error and roughly compensates the vco frequency. in this case, the afc id detects if the frequency difference continues for a period of 15h 6 (5760s), and afc id error is available only when the frequency difference continues for that period. the afc id also detects the existence of c sync. when the c sync is missing in various speed mode, the afc id cuts off its output and maintains the state immediately before the output cutout. the phase lock of the c sync and vco frequencies is carried out in the pll loop composed of the s/h and lpf circuits. 6. bell and c-bell filters the bell filter is applied to the secam color tv signal to suppress the level near the chrominance subcarrier (f or , f ob ). in rec mode, the cxa1203 employs the bell filter (having the inverted characteristics from the bell filter) to obtain the chrominance subcarrier of the same amplitude at every hue. the output signal from the bell filter is sent to the record signal processing block of chrominance signal in the cxa1200. in playback mode, the chrominance signal processed in the cxa1200 is input to the c-bell (having the same characteristics as the bell filter) filter of the cxa1203 to equalize the input signal with the secam color tv signal. the output from the c-bell filter is mixed with the y signal in the cxa1200 and sent to the cxa1201. the typical input level of the bell filter is 32mvp-p, and that of the c-bell filter is 83mvp-p. 7. secam detector circuit the secam detector circuit employed in the cxa1203 converts the chrominance subcarrier frequency ? 1 to a voltage, and detects the color system by the voltage variation: pal system if no voltage variation is present, or secam system if the voltage varies every 1h. when the color alignment is carried out in secam mode, the secam ack output (pin 3) is always set to high by inputting the secam jump output (pin 7) to the dldp (pin 6). ? 1 pal system: color burst signal (4.43361875mhz) secam system: line id signal f or : 4.40625mhz f ob : 4.25000mhz 5. f h pll hd vco s/h xshp c sync afc id lpf 1/2 1/2f h hd swd 1/2f h 11 10
22 cxa1203m/n fig. 9. application circuit 1 (for pal/secam mode) 5v 5v 5v 5v 5v 5v bpf 1k 1k 1k 0.01 20k 1k 20k 33k 2.2k 22k 1k 1k 1.5k 20k 100k 100k 100p 0.01 0.01 10p 1500p 5v 15k 390k 27k 33p 0.1 110p 0.01 0.01 0.022 39 820 100k 100k 1.2k 10 1 10 3.3 4.7 1000p 4.7k 1k 10k 10k jog rec/pb bell in secam in fsc in pb chroma out pb pb rec (se) pb (pal) pb (se) rec th/dl swd 1/2fhm th/dl (1/2fhta) pal-m bf bf pal-m pal cw bf xch th/dl (1/2fhta) dl th xpb mask 75 1 mask 75 2 u erri 1/2fhm pal-m th/dl xfhm 1/2fhm 1/2fhm sa cont clg pls clp pls swd 1/2fht 1/2 fht secam detpls test rst normal secam bell in secam in h id normal 1/2fhtab swd1/2fhm swd1/2fht d erri xshp mode c-bell bell amp 90 vco s/h peak hold lpf2 s/h 75% mask2 75% mask1 edge trig edge trig secam p. d. jump p. d. hd afc id d v-i1 2 sq p.d. lpf1 lpf cont clamp lpf1 fm demod lpf3 conv1 dummy lim lim1 lim2 v-i2 lpf2 sw main sw bf gen 75% 150% d 1/2 d bell filter 24 adj 23 bell in 22 mode 21 secam in 20 dl gain adj 19 fsc in 18 sq id 17 dl apc lpf 16 c out 15 iref 14 vreg 13 v cc 1 pb c in 2 secam ack 3 1/2fhmp 4 75% c 5 dldp 6 secam jump 7 secam lpf 8 afc lpf 9 hd 10 c sync 11 gnd 12 pb chroma in secam ack c sync vcc 20k application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
23 cxa1203m/n fig. 10. application circuit 2 (for pal mode only) 5v 5v 5v 5v 5v bpf 1k 1k 1k 0.01 20k 1k 20k 33k 2.2k 22k 1k 1k 1.5k 20k 100k 100k 100p 0.01 0.01 10p 1500p 110p 0.01 0.01 20k 100k 100k 10 1 10 4.7 1000p 4.7k 10k 10k jog rec/pb fsc in pb chroma out 20k pb pb rec (se) pb (pal) pb (se) rec th/dl swd 1/2fhm th/dl (1/2fhta) pal-m bf bf pal-m pal cw bf xch th/dl (1/2fhta) dl th xpb mask 75 1 mask 75 2 u erri 1/2fhm pal-m th/dl xfhm 1/2fhm 1/2fhm sa cont clg pls clp pls swd 1/2fht 1/2 fht secam detpls test rst normal secam bell in secam in h id normal 1/2fhtab swd1/2fhm swd1/2fht d erri xshp mode c-bell bell amp 90 vco s/h peak hold lpf2 s/h 75% mask2 75% mask1 edge trig edge trig secam p. d. jump p. d. hd afc id d v-i1 2 sq p.d. lpf1 lpf cont clamp lpf1 fm demod lpf3 conv1 dummy lim lim1 lim2 v-i2 lpf2 sw main sw bf gen 75% 150% d 1/2 d bell filter 24 adj 23 bell in 22 mode 21 secam in 20 dl gain adj 19 fsc in 18 sq id 17 dl apc lpf 16 c out 15 iref 14 vreg 13 v cc 1 pb c in 2 secam ack 3 1/2fhmp 4 75% c 5 dldp 6 secam jump 7 secam lpf 8 afc lpf 9 hd 10 c sync 11 gnd 12 pb chroma in c sync vcc application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
24 cxa1203m/n notes on use 1. phase adjustment in pal playback mode the phase of the ex burst signal can be adjusted with the phase of the input fsc (chrominance subcarrier). the phase of the dl signal can be adjusted by applying a current to pin 16. adjust the phase of the fsc so that the phase of the ex burst signal in jog playback mode matches the phase of the color burst signal in normal playback mode at the pb chroma output (pin 15). then, adjust the current to be applied to pin 16 so that the dl signal becomes symmetrical to the th signal about the b-y axis. 2. pal-m mode fig. 11 input an ntsc signal to pin 2, the fsc signal (3.58mhz) to pin 18 and the c sync signal (15.75mhz) to pin 11. then the pal-m playback signal is obtained at pb chroma output (pin 15). to adjust the phase, first input a burst signal with the same phase as the b-y axis, and adjust the phase of the fsc to be input so that the phase of the th signal matches the center phase of the ex burst at pin 15. then adjust the current to be applied to pin 16 so that the phase of the dl signal matches the center phase of the ex burst. in pal-m mode, pin 17 (sq id) should be fixed to "l". 3. pal only mode in pal only mode, a part of the secam detector block is turned off by fixing pin 22 (bell in) to "h". this reduces the current consumption to 1.2ma. the connections for other pins are the same as shown in "fig. 10 application circuit 2 (for pal mode only)". b-y r-y fsc th and dl signals ex burst b-y r-y output input fsc input signal
25 cxa1203m/n example of representative characteristics vreg supply voltage characteristic vcc (pin 1) [v] 4.50 4.21 4.22 4.23 4.24 4.25 4.75 5.00 5.25 5.50 vreg (pin 13) [v] th/dl/ex burst output level vs. ambient temperature ta ambient temperature [ c] 10 100 120 140 160 0 255075 output level [mvp-p] bell filter characteristic f frequency [mhz] 3.786 0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 4.286 4.786 vcc = 5.0v secam/rec mode input level: 32mvp-p (bell in) output: c out (pin 15) gain [db] c-bell filter characteristic f frequency [mhz] 3.786 0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 4.286 4.786 vcc = 5.0v secam/pb mode input level: 83mvp-p (bell in) output: c out (pin 15) vcc = 5.0v pal/pb mode input level: 150mvp-p (pb c in) fsc: 350mvp-p output: 4.43mhz bpf out (the output level is the average during 2h.) gain [db] dl th ex burst
26 cxa1203m/n phases of the hd and ex burst vs. ambient temperature relation of the phase of each pulse to the c sync signal ta ambient temperature [ c] 0 0 1.0 2.0 3.0 5.0 4.0 25 50 75 time [ s] sq det input/output vs. ambient temperature ta ambient temperature [ c] 40 60 80 100 120 0 255075 phase of the input signal [deg] th/dl/ex burst phases vs. ambient temperature ta ambient temperature [ c] 10 92 98 96 94 106 104 102 100 112 110 108 0 255075 phase [deg] vcc = 5.0v pal/pb mode input level: 150mvp-p (pb c in) fsc: 350mvp-p output: c out (pin 15) dl th ex burst vcc = 5.0v pal/reset mode input level: 150mvp-p (pb c in) fsc: 350mvp-p output: sq id (pin 17) output at pin 17 l h output at pin 17 h l the phase is the absolute value determined by measuring the center angle of the tl, dl or ex burst during 2h with reference to the fsc (at pin 18). the phase of the input signal is the absolute value of the phase delay to the fsc. this is determined by delaying the phase of the input signal to the fsc and measuring the phase delay when the output changes. a c b d a b cd c sync (pin 11) hd (pin 10) ex burst (pin 15)
27 cxa1203m/n cxa1203m kokubu ass'y sony code eiaj code jedec code m package structure molding compound lead treatment lead material package mass epoxy resin solder plating 42/copper alloy 24pin sop (plastic) 15.0 0.1 + 0.4 1 12 13 24 0.45 0.1 5.3 0.1 + 0.3 7.9 0.4 0.2 0.05 + 0.1 0.5 0.2 0.1 0.05 + 0.2 0.15 1.85 0.15 + 0.4 6.9 0.24 sop-24p-l01 sop024-p-0300 0.3g 1.27 sony code eiaj code jedec code m package structure molding compound lead treatment lead material package mass epoxy resin solder plating 42/copper alloy 24pin sop (plastic) 15.0 0.1 + 0.4 1 12 13 24 0.45 0.1 5.3 0.1 + 0.3 7.9 0.4 0.2 0.05 + 0.1 0.5 0.2 0.1 0.05 + 0.2 0.15 1.85 0.15 + 0.4 6.9 0.24 sop-24p-l01 sop024-p-0300 0.3g 1.27 lead plating specifications item lead material copper alloy solder composition sn-bi bi:1-4wt% plating thickness 5-18 m spec. package outline unit: mm
28 cxa1203m/n cxa1203n sony corporation sony code eiaj code jedec code ssop-24p-l01 p-ssop24-7.8x5.6-0.65 package material lead treatment lead material package mass epoxy resin palladium plating copper alloy package structure 0.1g 24pin ssop (plastic) 0.1 0.1 0 to 10 0.5 0.2 detail a ? 5.6 0.1 24 ? 7.8 0.1 13 0.65 12 1 7.6 0.2 0.1 1.25 0.1 + 0.2 a 0.13 m note: dimension " ? " does not include mold protrusion. 0.15 0.01 detail b : palladium + 0.03 b=0.22 0.03 b b package outline unit: mm

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